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Show Bid Request

Circuit Design Electrical Engineering EE Electronics - Project 3
Bid Request Id: 72090
Bookmark in my 'To Do' list
Posted by: cityworks (1 ratings)
(Software buyer rating 10)
Non-action Ratio: Very Good - 0.00%
Buyer Security Verifications: Unverified
Approved on: Jul 8, 2003
1:53:35 PM EDT
Bidding Closes: Jul 11, 2003
1:31:42 PM EDT
Viewed (by coders): 105 times
Deadline: 4 days.
Phase:
Cancelled
Max Accepted Bid: Bidding is closed
Project Type: Personal Project / Homework Help
Bidding Type: Open Auction
Categories: Misc
Enter chat room for this bid request
(1 active users at Jul 21, 2003 2:24:04 PM EDT)

Description:
There is total 4 problems... Here's the perview...

Problem 1
Design a 2-to-1 Multiplexor using Transmission-Gates (a pair of P- and N-channel transistors) and Inverter(s), by taking the following steps:
a) Design the truth table, design and draw the circuit schematic diagram.
b) Determine the size of transistors and state the criteria used in the determination.
c) Derive VoutL and VoutH by calculating the voltage drops through the Transmission gates (assuming the technology process data outlined in Chapter 6 Section4, and with CL = 0.2pF).
d) Design the physical layout (polygon) patterns following the design rules described in Chapter 6 and in the lectures, and try to minimize the over all layout area.
e) Draw a clean physical layout on a graph paper sheet using the following color map: Blue for metal layer, Black for contact, Red for Poly layer, Yellow for P - diffusion, and Green for N-diffusion. Label each signal terminal properly.
f) Assemble answer sheets behind this page according to the above order.
Problem 2
Design a positive edge-trigged (Master-Slave) D-type FlipFlop, with an asynchronous RESET, by taking the following steps.
a) Design the truth table, design and draw the circuit schematic diagram and justify the chosen circuit type in one paragraph with no more then 50 words.
b) Determine the size of transistors and state the criteria used in the determination.
c) Calculate the rise-time and fall-time (assuming the technology process data outlined in Chapter 6 Section4, and with CL = 0.2pF).
d) Design the physical layout (polygon) patterns following the design rules described in Chapter 6 and in the lectures, and try to minimize the over all layout area.
e) Draw a clean physical layout on a graph paper sheet using the following color map: Blue for metal layer, Black for contact, Red for Poly layer, Yellow for P - diffusion, and Green for N-diffusion. Label each signal terminal properly.
f) Assemble answer sheets behind this page according to the above order.

***************************************************

See All problems in Attachment

Deliverables:
1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.

2) Installation package that will install the software (in ready-to-run condition) on the platform(s) specified in this bid request.

3) Complete ownership and distribution copyrights to all work purchased.

4) Final Project should be scanned and then emailed.

Platform:
Windows

Additional Files:
This bid request includes IMPORTANT additional attached files. Please download and read fully before bidding.



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Name   Bid Amount 
 
Date   Coder Rating  


No bidding allowed, because this bid request was cancelled.

Cancelled Date: 7/21/2003 11:36:11 AM
Cancelled Reason:
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