Show Bid Request
Design a reduced combinational logic circuit
Bid Request Id: 28266
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Posted by: |
Hootie (8 ratings)
(Software buyer rating 10)
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Non-action Ratio: |
Very Good - 0.00%
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Buyer Security Verifications: |
Good
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Approved on: |
Sep 21, 2002 10:29:55 PM EDT
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Bidding Closes: |
Sep 22, 2002 10:50:00 PM EDT
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Viewed (by coders): |
157 times
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Deadline: |
9/23/2002
TIME EXPIRED
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Description:
Not really a code project, looking for some digital logic help with schematic drawing. : Design a code converter to convert a binary code to a 2-of-5 code. Use K-maps to reduce your circuit using the given inputs I3,I2,I1 and I0 to generate each output O4,O3,O2,O1 and O0. K-maps have been done with the following results: output 0: I3'I1'I0'+I2'I1'I0 output 1: I2'I0'+I2I1'I0 output 2: I3'I2'I1'I0+I1I0'+I1I2 output 3: I2I1'+I2I0'+I2'I1I0 output 4: I1I0+I3 Draw a schematic for each output using AND, OR, and NOT gates. If possible, share gates between schematics. 2-input gates have to be used.
Deliverables: 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.
2) Installation package that will install the software (in ready-to-run condition) on the platform(s) specified in this bid request.
3) Complete ownership and distribution copyrights to all work purchased.
Platform:
just need the schematics
Must be 100% finished and received by buyer on:
Sep 23, 2002 EDT
Deadline legal notes: All times are expressed in the time zone of the site EDT (UT - 5). If the buyer omitted a time, then the deadline is 11:59:59 PM EDT on the indicated date.
Special Conditions / Other:
must be completed by 12:00 noon EST on 23 Sept 2002
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Bidding/Comments:
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All monetary amounts on the site are in United States dollars.
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Name |
Bid Amount |
Date |
Coder Rating |
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N/A
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Sep 22, 2002 12:19:33 AM EDT
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9.4
(Superb)
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Is $40 OK with you?
Please reply asap... You need this within few hours ( a delay in reply will mean you are not interested in our bid...)
Regards |
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$30 (USD)
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Sep 22, 2002 1:07:35 AM EDT
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9.4
(Superb)
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Hello, we are already done with Kmap reduction of the first output : output 0: I3'I1'I0'+I2'I1'I0
(And there is a surprising result for the output atleast...)
Also when you say you want to use ONLY 2 input AND,OR and NOT, how can we, share gates between schematics?? Hope to complete with the drawing (will provide it in .bmp format...) in next 3 hours...
Amount negotiable...
Please reply asap...
Sincerely, VBMasterZ |
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