Show Bid Request
cache simulator
Bid Request Id: 12662
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Posted by: |
suebee1035 (1 ratings)
(Software buyer rating 10)
 ('Non-action' Ratio: None - 0%)
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Posted: |
Apr 4, 2002
1:50:56 PM EDT
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Bidding Closes: |
Apr 6, 2002
1:58:51 PM EDT
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Viewed (by coders): |
199 times
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Deadline: |
4/8/2002
TIME EXPIRED
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Description:
CDA3101 - Spring 2002
Chapter 7 Programming Assignment
Data Cache Simulator
Due at the beginning of class April 10, 2002
Responsible TA: T. Thomas
Your assignment is to write a program that simulates the behavior of a data cache. The program will
read a trace of references from standard input and produce statistics about the trace to standard output. The
grading process will include applying your simulator to multiple reference traces.
The cache simulator should first determine the configuration of the data cache. This is accomplished
by reading the configuration information on the first three lines of standard input. These lines specify the
number of cache sets, the number of elements of each set (associativity level), and the size of a cache line
in bytes. The format of the configuration is shown below (note that the values specified after the colon on
each line are the portion that can change). You may assume that the number of sets does not exceed 8192
and the associativity level does not exceed 8. You may also assume that the format and numbers specified
in these three lines are valid.
Number of sets: 8
Set size: 1
Line size: 4
The trace of references follow the configuration information and has the following format:
<accesstype>:<size>:<hexaddress>
where <accesstype> can be the characters:
R - indicates a read access
W - indicates a write access
<size> is the size of the reference in bytes (1,2,4, or 8), and <hexaddress> is the starting byte address of the
reference expressed as a hexadecimal number. You may assume that lines in the trace file conform to the
format, e.g., you do not have to check for lines that have an incorrect number of fields.
The example trace of references below, contains the addresses that correspond to the example references
described on page 547 and 548 of your text. Note the addresses here are hexadecimal byte addresses rather
than the decimal word addresses used in the text.
R:4:58
R:4:68
R:4:58
R:4:68
R:4:40
R:4:c
R:4:40
R:4:48
A file containing the cache configuration information and the trace data is available at
"http://www.cs.fsu.edu/˜gallivan/cda3101.html".
-1-
You can read the <accesstype>, <size>, and <hexaddress> into a character and two integers, respectively,
using formatted I/O with the following type of scanf statement.
scanf("%c:%d:%x", &accesstypevariable, &sizevariable, &hexaddressvariable);
Your cache simulator should use an LRU replacement algorithm. For data writ
Deliverables:
Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.
Complete copyrights to all work purchased.
Platform:
C++ or Visual C++
Must be 100% finished and received by buyer on:
Apr 8, 2002 EDT
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Bid Amount
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Date |
Coder Rating |
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This bid was accepted by the buyer!
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$29 (USD)
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Apr 4, 2002
3:33:34 PM EDT
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10
(Excellent)
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| Hello!
I find this project very nice. I just love to code simulators - just look at my projects list (in resume)! Ready to start ASAP.
It will be done in Visual C++ 6. Let me know if any graphical user interface needed.
Will be ready by sunday evening.
Support and help desk is included.
As usual I will send you fisrt available alpha version so you can review coding style, density of comments and stuff like that.
Sincerely yours,
Paul
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